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Master Thesis

Programmation et Utilisation du FPGA pour la validation et la vérification de circuits électroniques

Abstract : ST-Ericsson is a major actor of the semiconductor industry for mobile applications. It provides to his customers complete solutions as well as individual integrated circuits designed by its research and development teams. To validate the circuit design, in addition to the simulation phase, a verification stage on prototype is essential today before the product industrialization. This report focuses on the design of validation tool which offers the possibility to designers to verify if the digital part of the electronic circuit is working before the prototype manufacturing. The implementation of this solution was done thanks to the FPGA, a programmable circuit which allows emulating the behavior of the circuit. . The purpose of this work was to study the circuit to validate as well as the project where it had to be implemented. It was about to design digital filters which allow to use output signals of converter. The programming method used for the FPGA, consist of hardware description by graphical input. This design must include the test environment made with software and hardware tools.
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Master Thesis
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Submitted on : Monday, March 7, 2011 - 2:52:18 PM
Last modification on : Monday, February 21, 2022 - 3:38:12 PM
Long-term archiving on: : Wednesday, June 8, 2011 - 6:43:30 AM


  • HAL Id : dumas-00574220, version 1



Johanna Mariani. Programmation et Utilisation du FPGA pour la validation et la vérification de circuits électroniques. Electronique. 2011. ⟨dumas-00574220⟩



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