C. Hess and L. H. Weiland, Wafer level defect density distribution using checkerboard test structures, ICMTS 1998. Proceedings of 1998 International Conference on Microelectronic Test Structures (Cat. No.98CH36157), pp.101-106, 1998.
DOI : 10.1109/ICMTS.1998.688050

URL : http://goethe.ira.uka.de/ddg/icmt8l.pdf

C. and N. Berglung, A unified yield model incorporating both defect and parametric effects, IEEE Transactions on Semiconductor Manufacturing, vol.9, issue.3, pp.447-454, 1996.
DOI : 10.1109/66.536115