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Master Thesis Year : 2012

Exploiting Value Prediction With Quasi-Unlimited Resources

Arthur Perais


Recent trends regarding general purpose microprocessors have focused on Thread-Level Parallelism (TLP), and in general, on parallel architectures such as multicores. However, due to Amdahl's law, the gain to be had from the parallelization of a program is limited since there will always be an incompressible sequential part in the program. The execution time of this part only depends on the sequential performance of the processor the program is executed on. Value Prediction was proposed in the late 90's as a way to improve sequential performance by predicting instructions results, allowing the hardware to break data dependencies between instructions and thus extract more Instruction Level Parallelism (ILP) from the code. In the meantime, very accurate Geometric Length indirect branch target predictor such as ITTAGE were proposed. Indirect Branch Target Prediction and Value Prediction exhibit some similarities in concept, which is why we present a value predictor borrowing from both the Geometric Length indirect target branch predictor ITTAGE and existing work in the field of Value Prediction. As transistor budget is not expected to be a problem for future microprocessors, we study the behavior of the Value TAGE predictor for both finite and ''infinite'' sizes. We evaluate VTAGE performance on standard integer and floating-point workloads as well as on vectorized code.
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Dates and versions

dumas-00725221 , version 1 (24-08-2012)


  • HAL Id : dumas-00725221 , version 1


Arthur Perais. Exploiting Value Prediction With Quasi-Unlimited Resources. Hardware Architecture [cs.AR]. 2012. ⟨dumas-00725221⟩
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